Will graphene take the semiconductor industry towards the “Beyond CMOS” era?
The semiconductor industry is the cornerstone of today’s high-tech economy, with European semiconductor companies currently supporting more than 100,000 direct and a multitude of indirect jobs in Europe. With worldwide sales valued at US$ 340 billion in 2006, the sector supported a global market ~ US$ 1.3 trillion in terms of electronic systems, representing ~ 16% of the world market.
The continuous downsizing of components in ICT (Information and Communication Technology) has fuelled the electronics industry for the past three to four decades. This historic trend, known as Moore’s Law and manifested in the International Technology Roadmap for Semiconductors (ITRS), is currently facing increasingly complex technical challenges as well as economic constraints and it is expected that device physicists, process engineers and circuit designers will not be able to deliver downscaling solutions for more than 10-15 years. The methodology to reach the expected “end of the ITRS” has been named “More (of) Moore”. Nonetheless, improvements in computing performance and storage capacity beyond the limitations of current CMOS technology are expected to have a strong impact on future economic growth. This is generally acknowledged and a large number of experts from industry and academia have been consulted to conceive technological alternatives that can extend IT capabilities. Two prominent examples in Europe are the European Nanoelectronics Initiative Advisory Council (ENIAC) and the European Research Consortium for Informatics and Mathematics (ERCIM), which have both defined the post-“More of Moore” era as “Beyond CMOS”.
Within the GRAND project the objective of the project is the verification and assessment of a new material, graphene – monolayer or multilayer graphite sheets- towards its applicability for the fabrication of "Beyond CMOS" switches and local interconnects at nanoscale.
This key objective can be broken down into more specific questions:
• Can the key electronic properties of graphene (ballistic transport, high mobility) be maintained after on-chip integration?
• Can graphene withstand CMOS processing requirements?
• Is graphene technology scalable?
• How will graphene nanoribbons (GNRs) react to a CMOS environment?
• How will GNRs compare to carbon nanotubes (current density, metallic vs. Schottky contacts,..)?
• How can graphene be fabricated?
• What are realistic options for tuning the band gap?
• To what degree can atomistic models describe the reality accurately?
• Are simplified Monte Carlo simulations justified?
• How can transport in graphene be described and modelled?
While graphene research is considered a hot topic for exciting basic physical questions, the GRAND project is intended to act as a pathfinder for the ICT programme by focussing tightly on the generation of reliable data in a microelectronics context.
Project Fact Sheet
Project Reference: 215752 | Duration: 36 months |
Start date: 2008-01-01 | End date: 2010-12-31 |
Programme type: Seventh Framework Programme | Contract type: Collaborative project |
